To achieve higher processing speed, some computers have several independent execution units; some of these units arc capable of concurrently accessing a computer memory. These memories include cache memories for instruction and data storage that are sometimes used to achieve even faster execution speed.
Some prior art memory devices provide one single access port. However, other special memory circuits have been developed to support a plurality of access ports. These are used when multiple execution units in the computer demand several words of information at the same time. Such memories are normally known as multi-port memories.
Since some computers can execute several instructions concurrently, they need to be provided with more that one instruction word at a time. Instruction memories have been developed which are capable of providing a plurality of instruction words for each access operation. In one cycle, such memories, if properly addressed, are capable of providing a number of instructions equal to the number of words in a single memory line, i.e., where a memory line consists of a plurality of instruction words. For example, a cache memory can provide the information of all the words in a single word line when the address of the lowest word accessed corresponds to an exact multiple of the size of the cache memory line. Specifically, if a cache memory is organized in adjacent cache lines of four words (numbered from 0 to 3 within the line) and the lower two bits of the address correspond to zero, the full four words of the cache line can be read in one memory cycle operation. However, if the address of the accessed memory location modulo the size of the cache line is not zero, (i.e. assume 1 in this example), the memory reads a block of words fewer in number than the number of words in a full memory line (here four words) in one cycle. In this example, 3 words starting at position 1 in a first line are read in a first cycle. Then the remaining word(s) rounding out a full line (here 4) are read from a next word line in a subsequent cycle. In this example, one word starting at position 0 in the next line is read in the next cycle. Note that the prior art takes multiple cycles to read information from multiple cache lines if a Full cache line is demanded and the address modulo the size of the cache line is not equal to zero.
The prior art includes various ways to implement multi-port (specifically dual port) memory devices. Some dual-port memory devices use a plurality of word and bit lines to access the memory storage cells through independent electrical wires. This approach, as compared to a single port memory, normally requires a relatively larger area on silicon integrated circuits to accommodate the extra wires necessary. It also requires duplication of the sense amplifiers needed to read the memory content from the bit lines; one sense amplifier being needed for each set of bit lines. Other prior art dual port memory systems use interleaved memories. Interleaved memories have several blocks of independent single port memories. Interleaved dual-port memories can access different blocks in the same machine cycle if the addresses of the data to be read or written to are located in different blocks. If this is not the case (i.e. the two addresses are within the same block), information must be read or written from the same block and interleaved memories behave like a single port memory where two or more cycles are needed to access information. Interleaved memories do not need to use multiple sets of word and bit lines in a memory array, but they require duplication of other circuitry, such as address decoders, sense amplifiers and read/write control circuitry. Therefore, interleave memories, when implemented in integrated circuits, are typically less dense than single port memories of the same capacity.